A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT

Rei Chin Ju*, Jia Wei Chen, Jiun-In  Guo, Tien-Fu Chen

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

3 Scopus citations

Abstract

This paper proposes a parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT. For meeting different performance requirements, we provide a set of parameters in configuring the proposed IP generator including the types of DCT/IDCT architectures, the word-lengths of datapath, and the functions of transform. We adopt two different approaches in designing the 2-D DCT/IDCT including the high throughput adder-based approach and the low-cost group distributed arithmetic (GDA) approach, which exhibits different power dissipation and performance. In addition to generating the synthesizable VERILOG code and the associated supporting files for the IP core, the proposed power-aware IP generator can also perform the data precision analysis for users when trading-off the hardware cost, power consumption, and data precision in designing the DCT/IDCT IP for the portable multimedia applications.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
DOIs
StatePublished - 7 Sep 2004
Event2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada
Duration: 23 May 200426 May 2004

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