This paper presents a parameterized low power design for the one-dimensional discrete Fourier transform (DFT) of variable lengths. By combining the cyclic convolution formulation, block-based distributed arithmetic, dynamic pipeline technique, and Cooley-Tukey decomposition together, we have developed a parameterized hardware design for the DFT of variable lengths ranging from 256 to 4096 points and with different modes of performance, which facilitates the performance-driven design considerations in terms of power consumption and processing speeds. This feature is beneficial to developing a parameterized DFT Intellectual Property (IP) core for meeting the system requirements of different silicon-on-a-chip applications as compared with the existing fixed length DFT designs.
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 14 Jul 2003|
|Event||Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand|
Duration: 25 May 2003 → 28 May 2003