A parallel multi-pattern PRBS generator and BER tester for 40+ Gbps serdes applications

Wei-Zen Chen*, Guan Sheng Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

This paper presents the design of a programmable PRBS generator and a BER tester according to CCITT recommendations. Implemented in a parallel feedback configuration, this IC features PRBS generation of the sequences of length 27-l, 210-1, 215-1, 223-1, and 231-1 b for up to 40+Gbps serdes applications with 1:16 multiplexing and demultpilexing. The mark densities of 1/2, 1/4 and 1/8 for each of the patterns are also selectable. This IC could be used as a low cost substitute for more expensive bit error rate test system. Implemented in a 0.18 μm CMOS process, the total power dissipation is 141 mW.

Original languageEnglish
Title of host publicationProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
Pages318-321
Number of pages4
DOIs
StatePublished - 1 Dec 2004
EventProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits - Fukuoka, Japan
Duration: 4 Aug 20045 Aug 2004

Publication series

NameProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

Conference

ConferenceProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
CountryJapan
CityFukuoka
Period4/08/045/08/04

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