A parallel intelligent OPC technique for design and fabrication of VLSI circuit

Shao Ming Yu*, Yiming Li

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

We in this paper develop a parallel intelligent optical proximity correction technique for process distortion compensation of layout mask. This approach integrates an improved genetic algorithm, the rule- and model-based methods, and a parallel domain decomposition algorithm to perform the mask correction on a Linux-based PC cluster with message passing interface libraries. Testing on several fundamental patterns and application to VLSI circuits, this approach shows good correction accuracy and efficiency. Benchmark results, such as speedup, and parallel efficiency are achieved and exhibit excellent parallel performance. This is a constructive approach to developing advanced computer aided design tools for design and fabrication of integrated circuits.

Original languageEnglish
Title of host publication2005 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2005 Technical Proceedings
EditorsM. Laudon, B. Romanowicz
Pages724-727
Number of pages4
StatePublished - 2005
Event2005 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2005 - Anaheim, CA, United States
Duration: 8 May 200512 May 2005

Publication series

Name2005 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2005 Technical Proceedings

Conference

Conference2005 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2005
CountryUnited States
CityAnaheim, CA
Period8/05/0512/05/05

Keywords

  • CAD
  • Domain decomposition
  • Genetic algorithm
  • Lithography
  • Modeling and simulation
  • OPC
  • Parallel computing

Fingerprint Dive into the research topics of 'A parallel intelligent OPC technique for design and fabrication of VLSI circuit'. Together they form a unique fingerprint.

  • Cite this

    Yu, S. M., & Li, Y. (2005). A parallel intelligent OPC technique for design and fabrication of VLSI circuit. In M. Laudon, & B. Romanowicz (Eds.), 2005 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2005 Technical Proceedings (pp. 724-727). (2005 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2005 Technical Proceedings).