A p-v-n diode model for CMOS latchup

Hans P. Zappe*, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticle

2 Scopus citations

Abstract

A fully analytic model for holding voltage in a CMOS latch structure is derived by representing the device as a p-i-n or p-v-n diode. Due to heavy conductivity modulation in the region between emitters, this representation corresponds more closely to reality than lumped bipolar circuit equivalents, and requires no characterization of the parasitic latch components. Through considerations of the various current flows through the latch, an expression for the holding voltage as a function of emitter-emitter spacing is derived. Comparison with numerical simulation indicates adequate agreement.

Original languageEnglish
Pages (from-to)1275-1279
Number of pages5
JournalSolid State Electronics
Volume34
Issue number11
DOIs
StatePublished - 1 Jan 1991

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