A numerical model for simulating MOSFET gate current degradation by considering the interface state generation

C. M. Yih, Steve S. Chung, C. C.H. Hsu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

In this paper, a new gate current degradation model for n-MOSFET's by considering the interface state generation is proposed. This interface state has been characterized using a new approach and incorporated into a 2D device simulation for predicting the device gate current characteristics due to a hot carrier stress induced effect. Good agreement of the gate current has been achieved as compared with the measurement data for both fresh and stressed devices. This model is not only useful for predicting the gate current degradation, but also as a superior monitor to substrate current for submicron device reliability issues, in particular EPROM or flash EPROM devices.

Original languageEnglish
Title of host publication1996 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 1996
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages115-116
Number of pages2
ISBN (Electronic)0780327454
DOIs
StatePublished - 1 Jan 1996
Event1996 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 1996 - Tokyo, Japan
Duration: 2 Sep 19964 Sep 1996

Publication series

NameInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Conference

Conference1996 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 1996
CountryJapan
CityTokyo
Period2/09/964/09/96

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    Yih, C. M., Chung, S. S., & Hsu, C. C. H. (1996). A numerical model for simulating MOSFET gate current degradation by considering the interface state generation. In 1996 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 1996 (pp. 115-116). [865301] (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SISPAD.1996.865301