A Novel Technology Mapper for Complex Universal Gates

Meng Che Wu, Ai Quoc Dao, Mark Po Hung Lin

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Complex universal logic gates, which may have higher density and flexibility than basic logic gates and look-up tables (LUT), are useful for cost-effective or security-oriented VLSI design requirements. However, most of the technology mapping algorithms aim to optimize combinational logic with basic standard cells or LUT components. It is desirable to investigate optimal technology mappers for complex universal gates in addition to basic standard cells and LUT components. This paper proposes a novel technology mapper for complex universal gates with a tight integration of the following techniques: Boolean network simulation with permutation classification, supergate library construction, dynamic programming based cut enumeration, Boolean matching with optimal universal cell covering. Experimental results show that the proposed method outperforms the state-of-the-art technology mapper in ABC, in terms of both area and delay.

Original languageEnglish
Title of host publicationProceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages475-480
Number of pages6
ISBN (Electronic)9781450379991
DOIs
StatePublished - 18 Jan 2021
Event26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021 - Virtual, Online, Japan
Duration: 18 Jan 202121 Jan 2021

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
CountryJapan
CityVirtual, Online
Period18/01/2121/01/21

Keywords

  • complex universal gate
  • ECO
  • FPGA
  • Logic synthesis
  • structural ASIC
  • supergate library
  • technology mapping

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