A novel technique to fabricate 28 nm p-MOSFETs possessing gate oxide integrity on an embedded SiGe channel without silicon surface passivation

M. H. Yu*, M. H. Liao, T. C. Huang, L. T. Wang, T. L. Lee, S. M. Jang, Huang-Chung Cheng

*Corresponding author for this work

Research output: Contribution to journalArticle

5 Scopus citations

Abstract

A novel technique to create a suspending stacked gate oxide and subsequently to fill in an embedded SiGe channel (ESC) between the gate oxide and the underlying silicon substrate is proposed for the first time to fabricate 28 nm p-metal-oxide-semiconductor field-effect transistors (p-MOSFET). Without Si surface passivation on the ESC, such an ESC structure could achieve a p-FET transconductance (Gm) gain of 26% higher and a better I on-Ioff performance gain of 8% than that of conventional strained Si p-FETs with the source/drain (S/D) SiGe. Better S/D resistance (Rsd) in the resistance versus gate length plot and improved swing slope of the I d-Vgs plot indicates higher mobility in the ESC devices. Moreover, the off-state gate current of the ESC structure is also comparable to the conventional ones. From the x-ray photoelectron spectrum analysis, only the Si-O bonding, and no Ge-O bonding at the SiGe/SiO2 interface could account for this superior gate oxide integrity for the ESC and strained Si structure. Therefore, such a novel technique with an ESC structure is very promising for the 28 nm p-MOSFET devices era.

Original languageEnglish
Article number495102
JournalJournal of Physics D: Applied Physics
Volume45
Issue number49
DOIs
StatePublished - 12 Dec 2012

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