In this paper, a new architecture for digital image stabilizer (DIS) is presented. The system utilizes a matching algorithm on the Gray-coded bit-plane of the video sequence, which greatly reduces the complexity and enables the real-time processing capability in its motion estimating mechanism. According to the algorithm, a flexible system architecture containing software and hardware blocks is proposed. The proposed design is computationally efficient and is thus well suited as a low-cost solution for DIS in camcoders. In practice, the system has been validated on a mixed FPGA/DSP-based prototype.
|Number of pages||4|
|State||Published - 1 Dec 2000|
|Event||2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems - Tianjin, China|
Duration: 4 Dec 2000 → 6 Dec 2000
|Conference||2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems|
|Period||4/12/00 → 6/12/00|