A novel structure for digital image stabilizer

Guan Rong Chen*, Yeou Min Yeh, Sheng-Jyh Wang, Huang Cheng Chiang

*Corresponding author for this work

Research output: Contribution to conferencePaper

11 Scopus citations

Abstract

In this paper, a new architecture for digital image stabilizer (DIS) is presented. The system utilizes a matching algorithm on the Gray-coded bit-plane of the video sequence, which greatly reduces the complexity and enables the real-time processing capability in its motion estimating mechanism. According to the algorithm, a flexible system architecture containing software and hardware blocks is proposed. The proposed design is computationally efficient and is thus well suited as a low-cost solution for DIS in camcoders. In practice, the system has been validated on a mixed FPGA/DSP-based prototype.

Original languageEnglish
Pages101-104
Number of pages4
DOIs
StatePublished - 1 Dec 2000
Event2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems - Tianjin, China
Duration: 4 Dec 20006 Dec 2000

Conference

Conference2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems
CountryChina
CityTianjin
Period4/12/006/12/00

Fingerprint Dive into the research topics of 'A novel structure for digital image stabilizer'. Together they form a unique fingerprint.

  • Cite this

    Chen, G. R., Yeh, Y. M., Wang, S-J., & Chiang, H. C. (2000). A novel structure for digital image stabilizer. 101-104. Paper presented at 2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems, Tianjin, China. https://doi.org/10.1109/APCCAS.2000.913416