A novel self-aligned T-shaped gate process for deep submicron Si MOSFET's fabrication

Horng-Chih Lin*, Raymond Lin, Wen Fa Wu, Rong Ping Yang, Ming Shih Tsai, Tien-Sheng Chao, Tiao Yuan Huang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

T-shaped gate electrode is highly desired for high-speed FET fabrication since it can significantly reduce the gate resistance. In this study, we propose and demonstrate a self-aligned method of forming T-shaped gate which is suitable for ULSI Si-MOSFET's fabrication. This method employs CMP planarization, BOE selective etching and poly-Si sidewall spacer techniques to form the T-shaped poly-Si gate structure. Ti and Co silicidation were also incorporated to demonstrate the effectiveness of this process. Our experimental results indicate that the proposed process not only reduces the parasitic gate resistance, but also improves the thermal stability of the gate structure.

Original languageEnglish
Pages (from-to)26-28
Number of pages3
JournalIEEE Electron Device Letters
Volume19
Issue number1
DOIs
StatePublished - 1 Jan 1998

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