A novel self-aligned shallow trench isolation cell for 90nm 4Gbit NAND flash EEPROM s

Masayuki Ichige*, Yuji Takeuchi, Kikuko Sugimae, Atsuhiro Sato, Michiharu Matsui, Takeshi Kamigaichi, Hiroyuki Kutsukake, Yutaka Ishibashi, Masanobu Saito, Seiichi Mori, Hisataka Meguro, Shoichi Miyazaki, Tadashi Miwa, Shinya Takahashi, Tadashi Iguchi, Naoto Kawai, Susumu Tamon, Norihisa Arai, Hideyuki Kamata, Toshifumi MinamiHirohisa Iizuka, Masaaki Higashitani, Tuan Pham, Gertjan Hemink, Masaki Momodomi, Shirota Riichiro

*Corresponding author for this work

Research output: Contribution to journalConference article

10 Scopus citations

Abstract

A new self-aligned shallow trench isolation cell for 90 nm 4 Gbit NAND flash EEPROMs was discussed. Shallow trench isolation (STI) which is used to reduce memory cell size was also studied. It was found that this technology can be applied to 2 Gbit binary and 4 Gbit multi level memory cells.

Original languageEnglish
Pages (from-to)89-90
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
DOIs
StatePublished - 1 Oct 2003
Event2003 Symposium on VLSI Technology - Kyoto, Japan
Duration: 10 Jun 200312 Jun 2003

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    Ichige, M., Takeuchi, Y., Sugimae, K., Sato, A., Matsui, M., Kamigaichi, T., Kutsukake, H., Ishibashi, Y., Saito, M., Mori, S., Meguro, H., Miyazaki, S., Miwa, T., Takahashi, S., Iguchi, T., Kawai, N., Tamon, S., Arai, N., Kamata, H., ... Riichiro, S. (2003). A novel self-aligned shallow trench isolation cell for 90nm 4Gbit NAND flash EEPROM s. Digest of Technical Papers - Symposium on VLSI Technology, 89-90. https://doi.org/10.1109/VLSIT.2003.1221100