A new self-aligned shallow trench isolation cell for 90 nm 4 Gbit NAND flash EEPROMs was discussed. Shallow trench isolation (STI) which is used to reduce memory cell size was also studied. It was found that this technology can be applied to 2 Gbit binary and 4 Gbit multi level memory cells.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|State||Published - 1 Oct 2003|
|Event||2003 Symposium on VLSI Technology - Kyoto, Japan|
Duration: 10 Jun 2003 → 12 Jun 2003