This paper presents a simulation study of a novel self-aligned punchthrough implant. The self-aligned dopant profile is achieved using a high-energy implant after polysilicon gate definition. The result is that in the channel region the implant peak is just below the surface and in the source-drain regions the implant peak is well below the junctions. Performance is increased through the reduction of parasitic junction capacitance. In this analysis an established 0.5 μm baseline technology shows a 10% reduction in the delay of a loaded inverter. Technologies with smaller or larger gate dimensions can benefit as well.