A novel readout chip with extendability for multi-channel EEG measurement

Yi Chung Chen*, Chung Han Tsai, Zong Han Hsieh, Wai-Chi Fang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

This paper proposes an extendable front-end readout chip (EFRC) for electroencephalography (EEG) measurements. An EFRC is developed for EEG measurement with features including low power consumption, a high signal-to-noise ratio, and highly efficient chip area usage. A chopper-stabilized differential difference amplifier (CHDDA) is used in the first stage to amplify signals and then during another adjustable amplification stage and filter are used to process biomedical signals. A 10-bit successive approximation register analog-to-digital converter (SAR-ADC) then links to the back-end for digital signal processing. In the last stage, shift-register pairs are used to transmit data to the next chip and receive data from the previous chip. The shift register design allows the number of channels to be extended. A TSMC 0.18 um CMOS process is used to design the EFRC and it operates with a 1.8 V supply voltage. The results shows that the total power consumption for the EFRC chip is approximately 80.268 uW and the chip area is approximately 944 × 863 um2.

Original languageEnglish
Title of host publication2013 IEEE International Conference on Consumer Electronics, ICCE 2013
Pages236-237
Number of pages2
DOIs
StatePublished - 24 Apr 2013
Event2013 IEEE International Conference on Consumer Electronics, ICCE 2013 - Las Vegas, NV, United States
Duration: 11 Jan 201314 Jan 2013

Publication series

NameDigest of Technical Papers - IEEE International Conference on Consumer Electronics
ISSN (Print)0747-668X

Conference

Conference2013 IEEE International Conference on Consumer Electronics, ICCE 2013
CountryUnited States
CityLas Vegas, NV
Period11/01/1314/01/13

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