A novel poly-Si nanowire TFT for nonvolatile memory applications

Hsin Hwei Hsu*, Horng-Chih Lin, Jian Fu Huang, Tiao Yuan Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A novel ploy-Si nanowire TFT-SONOS device configured with independent double-gate structure was fabricated and characterized. The electrical characteristics including programming and erasing properties were studied. Adding an adequate top-gate bias was found to improve the programming efficiency, resulting in larger memory window.

Original languageEnglish
Title of host publication17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007
Pages55-56
Number of pages2
DOIs
StatePublished - 1 Dec 2007
Event17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007 - Taipei, Taiwan
Duration: 3 Dec 20075 Dec 2007

Publication series

NameRecords of the IEEE International Workshop on Memory Technology, Design and Testing
ISSN (Print)1087-4852

Conference

Conference17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007
CountryTaiwan
CityTaipei
Period3/12/075/12/07

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