A novel poly-Si nanowire TFT for nonvolatile memory applications

Hsin Hwei Hsu; Horng-Chih Lin; Jian Fu Huang; Tiao Yuan Huang

doi:10.1109/MTDT.2007.4547618

A novel poly-Si nanowire TFT for nonvolatile memory applications

Hsin Hwei Hsu^*, Horng-Chih Lin, Jian Fu Huang, Tiao Yuan Huang

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A novel ploy-Si nanowire TFT-SONOS device configured with independent double-gate structure was fabricated and characterized. The electrical characteristics including programming and erasing properties were studied. Adding an adequate top-gate bias was found to improve the programming efficiency, resulting in larger memory window.

Original language	English
Title of host publication	17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007
Pages	55-56
Number of pages	2
DOIs	https://doi.org/10.1109/MTDT.2007.4547618
State	Published - 1 Dec 2007
Event	17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007 - Taipei, Taiwan Duration: 3 Dec 2007 → 5 Dec 2007

Publication series

Name	Records of the IEEE International Workshop on Memory Technology, Design and Testing
ISSN (Print)	1087-4852

Conference

Conference	17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007
Country	Taiwan
City	Taipei
Period	3/12/07 → 5/12/07

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10.1109/MTDT.2007.4547618

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@inproceedings{700cfe898cba41718af37c04a81117d5,

title = "A novel poly-Si nanowire TFT for nonvolatile memory applications",

abstract = "A novel ploy-Si nanowire TFT-SONOS device configured with independent double-gate structure was fabricated and characterized. The electrical characteristics including programming and erasing properties were studied. Adding an adequate top-gate bias was found to improve the programming efficiency, resulting in larger memory window.",

author = "Hsu, {Hsin Hwei} and Horng-Chih Lin and Huang, {Jian Fu} and Huang, {Tiao Yuan}",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/MTDT.2007.4547618",

language = "English",

isbn = "9781424416561",

series = "Records of the IEEE International Workshop on Memory Technology, Design and Testing",

pages = "55--56",

booktitle = "17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007",

note = "null ; Conference date: 03-12-2007 Through 05-12-2007",

}

Hsu, HH, Lin, H-C, Huang, JF & Huang, TY 2007, A novel poly-Si nanowire TFT for nonvolatile memory applications. in 17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007., 4547618, Records of the IEEE International Workshop on Memory Technology, Design and Testing, pp. 55-56, 17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007, Taipei, Taiwan, 3/12/07. https://doi.org/10.1109/MTDT.2007.4547618

A novel poly-Si nanowire TFT for nonvolatile memory applications. / Hsu, Hsin Hwei; Lin, Horng-Chih; Huang, Jian Fu; Huang, Tiao Yuan.

17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007. 2007. p. 55-56 4547618 (Records of the IEEE International Workshop on Memory Technology, Design and Testing).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A novel poly-Si nanowire TFT for nonvolatile memory applications

AU - Hsu, Hsin Hwei

AU - Lin, Horng-Chih

AU - Huang, Jian Fu

AU - Huang, Tiao Yuan

PY - 2007/12/1

Y1 - 2007/12/1

N2 - A novel ploy-Si nanowire TFT-SONOS device configured with independent double-gate structure was fabricated and characterized. The electrical characteristics including programming and erasing properties were studied. Adding an adequate top-gate bias was found to improve the programming efficiency, resulting in larger memory window.

AB - A novel ploy-Si nanowire TFT-SONOS device configured with independent double-gate structure was fabricated and characterized. The electrical characteristics including programming and erasing properties were studied. Adding an adequate top-gate bias was found to improve the programming efficiency, resulting in larger memory window.

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U2 - 10.1109/MTDT.2007.4547618

DO - 10.1109/MTDT.2007.4547618

M3 - Conference contribution

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SN - 9781424416561

T3 - Records of the IEEE International Workshop on Memory Technology, Design and Testing

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BT - 17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007

Y2 - 3 December 2007 through 5 December 2007

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A novel poly-Si nanowire TFT for nonvolatile memory applications

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