A novel model for on-chip heat dissipation

Her-Ming Chiueh*, Jeffrey Draper, Louis Luh, John Choma

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

10 Scopus citations

Abstract

This paper presents an analytical model for on-chip heat dissipation in VLSI design. A chip and its test configuration also are developed to verify modeling results. The model and chip are representative of general IC packages. Our research shows that circuit location on a chip determines its default offset temperature and heat transport properties, which must be considered for accurate prediction of junction temperature and electrothermal analysis. The model yields insights about on-chip heat dissipation, which are very useful for mixed-signal VLSI designs and circuit reliability analysis.

Original languageEnglish
Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems - Proceedings
PublisherIEEE
Pages779-782
Number of pages4
ISBN (Print)0780351460
DOIs
StatePublished - 1 Dec 1998
EventProceedings of the 1998 IEEE Asia-Pacific Conference on Circuits and Systems - Microelectronics and Integrating Systems (IEEE APCCAS-98) - Chiangmai, Thailand
Duration: 24 Nov 199827 Nov 1998

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems - Proceedings

Conference

ConferenceProceedings of the 1998 IEEE Asia-Pacific Conference on Circuits and Systems - Microelectronics and Integrating Systems (IEEE APCCAS-98)
CityChiangmai, Thailand
Period24/11/9827/11/98

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