A novel LTPS-TFT-based charge-trapping memory device with field-enhanced nanowire structure

Ta Chuan Liao*, Sheng Kai Chen, Ming H. Yu, Chun Yu Wu, Tsung Kuei Kang, Feng Tso Chien, Yen Ting Liu, Chia Min Lin, Huang-Chung Cheng

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

12 Scopus citations

Abstract

A novel gate-all-around low-temperature poly-Si (LTPS) thin-film transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory with field-enhanced nanowire (FEN) structure has been proposed to improve the program and erase (P/E) performance. Each nanowire inherently had three sharp corners fabricated simply by sidewall spacer formation to obtain high local electric fields. The fieldenhanced carrier tunneling via such a structure led to faster P/E speed and wider memory window for the FEN-TFT SONOS as compared to the conventional planar (CP) counterpart. The improvement was also further verified with the simulation results. Such a high-performance FEN-TFT SONOS memory with process simplicity is very suitable for future system-on-panel (SOP) applications.

Original languageEnglish
Title of host publication2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest
DOIs
StatePublished - 1 Dec 2009
Event2009 International Electron Devices Meeting, IEDM 2009 - Baltimore, MD, United States
Duration: 7 Dec 20099 Dec 2009

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference2009 International Electron Devices Meeting, IEDM 2009
CountryUnited States
CityBaltimore, MD
Period7/12/099/12/09

Fingerprint Dive into the research topics of 'A novel LTPS-TFT-based charge-trapping memory device with field-enhanced nanowire structure'. Together they form a unique fingerprint.

Cite this