A novel low-temperature polysilicon thin-film transistors with a self-aligned gate and raised source/drain formed by the damascene process

Kow-Ming Chang; Gin Min Lin; Guo Liang Yang

doi:10.1109/LED.2007.903313

A novel low-temperature polysilicon thin-film transistors with a self-aligned gate and raised source/drain formed by the damascene process

Kow-Ming Chang^*, Gin Min Lin, Guo Liang Yang

^*Corresponding author for this work

National Chiao Tung University

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

In this letter, a novel structure of the polycrystalline silicon thin-film transistors (TFTs) with a self-aligned gate and raised source/ drain (RSD) formed by the damascene process has been developed and investigated. Comparing with the conventional coplanar TFT, the proposed RSD TFT has a remarkable lower off-state current (177 to 6.29 nA), and the on/off current ratio is only slightly decreased from 1.71 times 10 ⁷ to 1.39 times 10 ⁷ . Only four photomasking steps are required. This novel structure is an excellent candidate for further high-performance large-area device applications.

Original language	English
Pages (from-to)	806-808
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	28
Issue number	9
DOIs	https://doi.org/10.1109/LED.2007.903313
State	Published - 1 Dec 2007

Keywords

Damascene process
Four masks
On/off current ratio
Polycrystalline silicon thin-film transistor (poly-Si TFT)
Raised source/drain (RSD)
Self-aligned gate
Thin channel

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title = "A novel low-temperature polysilicon thin-film transistors with a self-aligned gate and raised source/drain formed by the damascene process",

abstract = " In this letter, a novel structure of the polycrystalline silicon thin-film transistors (TFTs) with a self-aligned gate and raised source/ drain (RSD) formed by the damascene process has been developed and investigated. Comparing with the conventional coplanar TFT, the proposed RSD TFT has a remarkable lower off-state current (177 to 6.29 nA), and the on/off current ratio is only slightly decreased from 1.71 times 10 7 to 1.39 times 10 7 . Only four photomasking steps are required. This novel structure is an excellent candidate for further high-performance large-area device applications.",

keywords = "Damascene process, Four masks, On/off current ratio, Polycrystalline silicon thin-film transistor (poly-Si TFT), Raised source/drain (RSD), Self-aligned gate, Thin channel",

author = "Kow-Ming Chang and Lin, {Gin Min} and Yang, {Guo Liang}",

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AU - Chang, Kow-Ming

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PY - 2007/12/1

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AB - In this letter, a novel structure of the polycrystalline silicon thin-film transistors (TFTs) with a self-aligned gate and raised source/ drain (RSD) formed by the damascene process has been developed and investigated. Comparing with the conventional coplanar TFT, the proposed RSD TFT has a remarkable lower off-state current (177 to 6.29 nA), and the on/off current ratio is only slightly decreased from 1.71 times 10 7 to 1.39 times 10 7 . Only four photomasking steps are required. This novel structure is an excellent candidate for further high-performance large-area device applications.

KW - Damascene process

KW - Four masks

KW - On/off current ratio

KW - Polycrystalline silicon thin-film transistor (poly-Si TFT)

KW - Raised source/drain (RSD)

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KW - Thin channel

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