A novel high-performance poly-silicon thin film transistor with a self-aligned thicker sub-gate oxide near the drain/source regions

Kow-Ming Chang, Hung Chung Yuan Hung Chung, Ming Lin Gin Ming Lin, Hong Lin Jian Hong Lin, Gun Deng Chi Gun Deng

Research output: Contribution to journalArticle

10 Scopus citations

Abstract

In this letter, a novel high-performance poly-silicon thin-film transistor (poly-Si TFT) with a self-aligned thicker sub-gate oxide near the drain/source regions is proposed. Poly-Si TFTs with tiffs new structure have been successfully fabricated and the results demonstrate a higher on-off current ratio of 5.9 × 106 and also shows the off-state leakage current 100 times lower than those of the conventional ones at VGS = -15 V and VDS = 10 V. Only four photo-masking steps are required and fully compatible with the conventional TFT fabrication processes. This novel structure is a good candidate for the further high-performance large-area device applications.

Original languageEnglish
Pages (from-to)472-474
Number of pages3
JournalIEEE Electron Device Letters
Volume22
Issue number10
DOIs
StatePublished - 1 Oct 2001

Keywords

  • On-off current ratio
  • Photo-masking steps
  • Poly-silicon thin-film transistor
  • Self-aligned thicker sub-gate oxide

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    Chang, K-M., Yuan Hung Chung, H. C., Gin Ming Lin, M. L., Jian Hong Lin, H. L., & Chi Gun Deng, G. D. (2001). A novel high-performance poly-silicon thin film transistor with a self-aligned thicker sub-gate oxide near the drain/source regions. IEEE Electron Device Letters, 22(10), 472-474. https://doi.org/10.1109/55.954915