A novel high-performance poly-silicon thin film transistor with a self-aligned thicker sub-gate oxide near the drain/source regions

Kow-Ming Chang; Hung Chung Yuan Hung Chung; Ming Lin Gin Ming Lin; Hong Lin Jian Hong Lin; Gun Deng Chi Gun Deng

doi:10.1109/55.954915

A novel high-performance poly-silicon thin film transistor with a self-aligned thicker sub-gate oxide near the drain/source regions

Kow-Ming Chang, Hung Chung Yuan Hung Chung, Ming Lin Gin Ming Lin, Hong Lin Jian Hong Lin, Gun Deng Chi Gun Deng

National Chiao Tung University

Research output: Contribution to journal › Article › peer-review

10 Scopus citations

Abstract

In this letter, a novel high-performance poly-silicon thin-film transistor (poly-Si TFT) with a self-aligned thicker sub-gate oxide near the drain/source regions is proposed. Poly-Si TFTs with tiffs new structure have been successfully fabricated and the results demonstrate a higher on-off current ratio of 5.9 × 10⁶ and also shows the off-state leakage current 100 times lower than those of the conventional ones at V_GS = -15 V and V_DS = 10 V. Only four photo-masking steps are required and fully compatible with the conventional TFT fabrication processes. This novel structure is a good candidate for the further high-performance large-area device applications.

Original language	English
Pages (from-to)	472-474
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	22
Issue number	10
DOIs	https://doi.org/10.1109/55.954915
State	Published - 1 Oct 2001

Keywords

On-off current ratio
Photo-masking steps
Poly-silicon thin-film transistor
Self-aligned thicker sub-gate oxide

Access to Document

10.1109/55.954915

Link to publication in Scopus

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title = "A novel high-performance poly-silicon thin film transistor with a self-aligned thicker sub-gate oxide near the drain/source regions",

abstract = "In this letter, a novel high-performance poly-silicon thin-film transistor (poly-Si TFT) with a self-aligned thicker sub-gate oxide near the drain/source regions is proposed. Poly-Si TFTs with tiffs new structure have been successfully fabricated and the results demonstrate a higher on-off current ratio of 5.9 × 106 and also shows the off-state leakage current 100 times lower than those of the conventional ones at VGS = -15 V and VDS = 10 V. Only four photo-masking steps are required and fully compatible with the conventional TFT fabrication processes. This novel structure is a good candidate for the further high-performance large-area device applications.",

keywords = "On-off current ratio, Photo-masking steps, Poly-silicon thin-film transistor, Self-aligned thicker sub-gate oxide",

author = "Kow-Ming Chang and {Yuan Hung Chung}, {Hung Chung} and {Gin Ming Lin}, {Ming Lin} and {Jian Hong Lin}, {Hong Lin} and {Chi Gun Deng}, {Gun Deng}",

year = "2001",

month = oct,

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journal = "IEEE Electron Device Letters",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

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A novel high-performance poly-silicon thin film transistor with a self-aligned thicker sub-gate oxide near the drain/source regions. / Chang, Kow-Ming; Yuan Hung Chung, Hung Chung; Gin Ming Lin, Ming Lin; Jian Hong Lin, Hong Lin; Chi Gun Deng, Gun Deng.

In: IEEE Electron Device Letters, Vol. 22, No. 10, 01.10.2001, p. 472-474.

Research output: Contribution to journal › Article › peer-review

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AU - Jian Hong Lin, Hong Lin

AU - Chi Gun Deng, Gun Deng

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AB - In this letter, a novel high-performance poly-silicon thin-film transistor (poly-Si TFT) with a self-aligned thicker sub-gate oxide near the drain/source regions is proposed. Poly-Si TFTs with tiffs new structure have been successfully fabricated and the results demonstrate a higher on-off current ratio of 5.9 × 106 and also shows the off-state leakage current 100 times lower than those of the conventional ones at VGS = -15 V and VDS = 10 V. Only four photo-masking steps are required and fully compatible with the conventional TFT fabrication processes. This novel structure is a good candidate for the further high-performance large-area device applications.

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