A novel fully self-aligned process for high cell density trench gate power MOSFETs

Bing-Yue Tsui*, Tian Choy Gan, Ming Da Wu, Hui Hua Chou, Zhi Liang Wu, Ching Tzong Sune

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

2 Scopus citations

Abstract

A novel self-aligned process for high cell density trench gate power MOSFETs with only four mask layers was proposed. The specific on-resistance can be as low as 0.21 mΩ-cm2 with 1.5um cell pitch and 35V breakdown voltage. Because this process shrinks trench space but not trench width, the quasi-saturation phenomenon is lighter. After optimization the thickness of n- drift layer and n+ substrate, specific on-resistance lower than 0.1 mΩ-cm2 with 0.6um technology could be expected.

Original languageEnglish
Pages205-208
Number of pages4
StatePublished - 18 Oct 2004
EventProceedings of the 16th International Symposium on Power Semiconductor Devices and ICs (ISPSD'04) - Kitakyushu, Japan
Duration: 24 May 200427 May 2004

Conference

ConferenceProceedings of the 16th International Symposium on Power Semiconductor Devices and ICs (ISPSD'04)
CountryJapan
CityKitakyushu
Period24/05/0427/05/04

Fingerprint Dive into the research topics of 'A novel fully self-aligned process for high cell density trench gate power MOSFETs'. Together they form a unique fingerprint.

Cite this