A novel fully CMOS process compatible PREM for SOC applications

C. C. Yeh*, Ta-Hui Wang, W. J. Tsai, T. C. Lu, Y. Y. Liao, N. K. Zous, C. Y. Chin, Y. R. Chen, M. S. Chen, Wen Chi Ting, Chih Yuan Lu

*Corresponding author for this work

Research output: Contribution to journalArticle

2 Scopus citations


A novel nonvolatile memory cell named programmable resistor with eraseless memory (PREM) is proposed for system on chip applications for the first time. PREM combines a novel "eraseless" algorithm and the progressive breakdown of an ultrathin oxide. No or one extra mask is needed with a standard CMOS process. Multitime programming, multilevel cell, nonvolatility, and low-voltage operation are realized. Good reliability is demonstrated based on the result of a single cell.

Original languageEnglish
Pages (from-to)203-204
Number of pages2
JournalIEEE Electron Device Letters
Issue number3
StatePublished - 1 Mar 2005


  • Eraseless
  • Multilevel cell (MLC)
  • Multitime programming (MTP)
  • Nonvolatile
  • Programmable resistor with eraseless memory (PREM)
  • Progressive breakdown
  • System on chip (SOC)

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    Yeh, C. C., Wang, T-H., Tsai, W. J., Lu, T. C., Liao, Y. Y., Zous, N. K., Chin, C. Y., Chen, Y. R., Chen, M. S., Ting, W. C., & Lu, C. Y. (2005). A novel fully CMOS process compatible PREM for SOC applications. IEEE Electron Device Letters, 26(3), 203-204. https://doi.org/10.1109/LED.2005.843221