A novel erase scheme to suppress overerasure in a scaled 2-bit nitride storage flash memory cell

Chih Chieh Yeh*, Ta-Hui Wang, Wen Jer Tsai, Tao Cheng Lu, Yi Ying Liao, Hung Yueh Chen, Nian Kai Zous, Wenchi Ting, Joseph Ku, Chih Yuan Lu

*Corresponding author for this work

Research output: Contribution to journalArticle

7 Scopus citations

Abstract

The cause of over-erasure in a two-bit nitride storage Flash memory cell is investigated. Extra positive charges accumulated above the n+ junction and channel-shortening enhanced drain-induced barrier lowering effect are found to be responsible for threshold voltage (Vt) lowering in an over-erased cell. A modified erase scheme is proposed to resolve this issue. By applying a source voltage during erase, the erase speed can be well controlled for cells with different channel lengths and a wide range of program-state Vt distribution, which will reduce overerasure significantly.

Original languageEnglish
Pages (from-to)643-645
Number of pages3
JournalIEEE Electron Device Letters
Volume25
Issue number9
DOIs
StatePublished - 1 Sep 2004

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    Yeh, C. C., Wang, T-H., Tsai, W. J., Lu, T. C., Liao, Y. Y., Chen, H. Y., Zous, N. K., Ting, W., Ku, J., & Lu, C. Y. (2004). A novel erase scheme to suppress overerasure in a scaled 2-bit nitride storage flash memory cell. IEEE Electron Device Letters, 25(9), 643-645. https://doi.org/10.1109/LED.2004.833596