To reduce the bandwidth requirement and the size of frame memory for video decoding, embedding a compressor/decompressor on the chip is a well-known solution. Video compression has been developed for a long time and numbers of algorithm have been proposed. Those algorithms show us that enhancing the complexity can reach better performance. However, algorithm with higher complexity is more difficult to be embedded in a video decoder system. Longer coding cycles and lager gate counts may become a heavy load of the original system. In this paper, a new embedded compressor/decompressor algorithm is proposed for H.264 video compression. It is a lossy compression formed by two dimensions discrete cosine transform and modified bit plane zonal coding. The proposed algorithm compresses the 4x4 size block into a 64 bits segment, and decompresses a frame into 4x4 blocks. The compression ratio is fixed at two. With pipelined architecture, it takes 72 cycles and 34 cycles per MB for encoding and decoding respectively. As a result, our proposal becomes flexible to be embedded with any video coding system to save power consumption while maintaining acceptable video quality.