In this study, we report a novel driving method to operate the amorphous silicon gate (ASG) driver circuits in flat panel display. The principal modification is to change the type of the clock signals to two low levels in the ASG circuit. The proposed ASG driver circuit has been implemented using a five-mask amorphous silicon process for thin-film transistors. The fall time of the output in the tested ASG circuit with the novel driving method is about 30% shorter than that with the conventional driving method. Moreover, the minimum operation high voltage keeps the same level of the ASG circuit with the new clock driving. Notably, the proposed driving method causes merely 5.5% increment of the power consumption, compared with the conventional one.
- Amorphous silicon gate (ASG) driver
- driving method
- fall time
- flat panel display (FPD)
- minimum operation high voltage