A novel double-gated nanowire TFT and investigation of its size dependency

Wei Chen Chen*, Chuan Ding Lin, Horng-Chih Lin, Tiao Yuan Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

A simple method for fabricating poly-Si nanowire (NW) TFT with multiple gates is proposed and characterized. In this structure, NW is formed mainly using both anisotropic and highly selective isotropic plasma etching. It is found that when the size of NW is scaled down, double-gated operation provides more improvement. Furthermore, by utilizing this unique independent double-gated configuration, the function of threshold voltage modulation is investigated.

Original languageEnglish
Title of host publication2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09
Pages121-122
Number of pages2
DOIs
StatePublished - 1 Dec 2009
Event2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09 - Hsinchu, Taiwan
Duration: 27 Apr 200929 Apr 2009

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings

Conference

Conference2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09
CountryTaiwan
CityHsinchu
Period27/04/0929/04/09

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