A novel digital etch technique for p-GaN gate HEMT

Yuan Lin, Yueh Chin Lin, Franky Lumbantoruan, Chang Fu Dec, Burhanuddin Yeop Majilis, Edward Yi Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

We demonstrate the digital etching (DE) process to fabricated E-mode p-GaN/AIGaN/GaN HEMT. DE process comprising low power oxygen (02) plasma oxidizing and low power boron trichloride (BCl3) plasma etching to selectively remove p-GaN layer. The atomic layer etching (ALE) has an etching rate of 1.62 nm/cycle to achieved depth of 70nm. The 5-μm source-drain offset length (LSD) device with Ni/Au gate metal demonstrated 365 mAlmm drain current density with threshold voltage (VTH) of +1.8V, on/off current ratio of 1.6×106, breakdown voltage (BV) of 154V, and static on-resistance (RON) of 8.47 Ω.mm. The 20-μm LSD device with Ni/Au gate metal demonstrated 211 mA/mm drain current density with VTH of +2V, and on/off current ratio of 1. 2×106, BV of 426V, and static RON of 17.3 Ω.mm.

Original languageEnglish
Title of host publication2018 IEEE International Conference on Semiconductor Electronics, ICSE 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages121-123
Number of pages3
ISBN (Electronic)9781538652831
DOIs
StatePublished - 3 Oct 2018
Event13th IEEE International Conference on Semiconductor Electronics, ICSE 2018 - Kuala Lumpur, Malaysia
Duration: 15 Aug 201817 Aug 2018

Publication series

NameIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
Volume2018-August

Conference

Conference13th IEEE International Conference on Semiconductor Electronics, ICSE 2018
CountryMalaysia
CityKuala Lumpur
Period15/08/1817/08/18

Keywords

  • AlGaN/GaN
  • Atomic layer etching
  • Digital Etching
  • E-mode
  • HEMT
  • Normally-off
  • p-GaN

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