A novel design flow for dummy fill using Boolean mask operations

Tseng Chin Luo*, Chia-Tso Chao, Philip A. Fisher, Chun Ren Kuo

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

Dummy fill has been demonstrated to be an effective technique to reduce process variation and improve manufacturability for advanced integrated circuit (IC) designs. However, the computation load, often several days for a realistic IC design, is a significant portion of the cycle time for delivering first silicon on new or modified designs. In this paper, we propose a novel design flow and dummy-fill algorithm based on Boolean operations, which greatly improves computational efficiency and pattern density uniformity, and enables dummy generation to be combined with the mask-preparation Boolean operations performed by the mask-fabrication facility. Mask data preparation can be performed in parallel with dummy generation and post-dummy simulation checks at the design house, resulting in improved first-silicon cycle time. Experimental results demonstrate these benefits in the context of an advanced foundry process technology.

Original languageEnglish
Article number6166347
Pages (from-to)468-479
Number of pages12
JournalIEEE Transactions on Semiconductor Manufacturing
Volume25
Issue number3
DOIs
StatePublished - 13 Aug 2012

Keywords

  • Boolean operation
  • dummy fill

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