A novel approach using discrete grain-boundary traps to study the variability of 3-D vertical-gate NAND flash memory cells

Pei Yu Wang, Bing-Yue Tsui

Research output: Contribution to journalArticlepeer-review

11 Scopus citations

Abstract

The 3-D NAND flash memory architectures will be a future trend, because they provide high memory capacity without aggressively scaling down. A vertical-gate (VG) structure composed of polysilicon (poly-Si) channels is a promising 3-D structure that could facilitate realizing an extremely tight-pitch NAND flash memory cell with high memory capacity. However, the variability of the VG memory cell induced by grain boundaries in the poly-Si channels is a major concern for aggressively scaled-down memory cells. In this paper, a discrete-trap approach is applied to emulate the real trap effects in a 3-D memory cell, and the 3-D structure geometry effects and the variation in the threshold voltage (VT) induced by the discrete grain-boundary traps are studied. Various Δ VT behaviors related to the structure geometry and trap position are examined. The effect of varying the body thickness on the Δ VT is stronger than that of varying the channel width. This paper presents various cases for using the discrete-trap approach to study the variability of VT in 3-D VG memory cells.

Original languageEnglish
Article number7122329
Pages (from-to)2488-2493
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume62
Issue number8
DOIs
StatePublished - 1 Aug 2015

Keywords

  • Flash memory
  • grain boundaries
  • polysilicon (poly-Si)
  • variability
  • vertical gate (VG).

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