A novel approach to generate self-aligned Ge/SiO2/SiGe gate-stacking structures in a single fabrication step

Wei Ting Lai, Kuo Ching Yang, Ting Chia Hsu, Po Hsiang Liao, Thomas George, Pei-Wen Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

We demonstrated a novel, self-aligned gate-stack heterostructure of Ge-quantum dot (QD)/SiO2/SiGe-shell on Si with superior interfacial properties in a single step of selective oxidation of a SiGe pillar over a Si3N4 buffer layer on Si substrate. Ge metal-oxide-semiconductor (MOS) capacitors exhibit a quite low interface trap density on the order of 1011 cm-2eV-1, and Ge n-MOSFETs show good turn on and off features with a subthreshld slope of 175 mV/dec and Ion/Ioff > 106.

Original languageEnglish
Title of host publication2014 Silicon Nanoelectronics Workshop, SNW 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479956777
DOIs
StatePublished - 4 Dec 2015
EventSilicon Nanoelectronics Workshop, SNW 2014 - Honolulu, United States
Duration: 8 Jun 20149 Jun 2014

Publication series

Name2014 Silicon Nanoelectronics Workshop, SNW 2014

Conference

ConferenceSilicon Nanoelectronics Workshop, SNW 2014
CountryUnited States
CityHonolulu
Period8/06/149/06/14

Fingerprint Dive into the research topics of 'A novel approach to generate self-aligned Ge/SiO<sub>2</sub>/SiGe gate-stacking structures in a single fabrication step'. Together they form a unique fingerprint.

Cite this