Abstract
A noise optimization formulation for a CMOS low-noise amplifier (LNA) with on-chip low-Q inductors is presented, which incorporates the series resistances of the on-chip low-Q inductors into the noise optimization procedure explicitly. A 10-GHz LNA is designed and implemented in a standard mixed-signal/RF bulk 0.18-μm CMOS technology based on this formulation. The measurement results, with a power gain of 11.25 dB and a noise figure (NF) of 2.9 dB, show the lowest NF among the LNAs using bulk 0.18-μm CMOS at this frequency.
Original language | English |
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Pages (from-to) | 1554-1559 |
Number of pages | 6 |
Journal | IEEE Transactions on Microwave Theory and Techniques |
Volume | 54 |
Issue number | 4 |
DOIs | |
State | Published - 1 Apr 2006 |
Keywords
- CMOS
- Low-noise amplifier (LNA)