A noise optimization formulation for CMOS low-noise amplifiers with on-chip low-Q inductors

Kuo Jung Sun; Zuo-Min Tsai; Kun You Lin; Huei Wang

doi:10.1109/TMTT.2006.871365

A noise optimization formulation for CMOS low-noise amplifiers with on-chip low-Q inductors

Kuo Jung Sun^*, Zuo-Min Tsai , Kun You Lin, Huei Wang

^*Corresponding author for this work

Institute of Communications Engineering

Research output: Contribution to journal › Article › peer-review

42 Scopus citations

Abstract

A noise optimization formulation for a CMOS low-noise amplifier (LNA) with on-chip low-Q inductors is presented, which incorporates the series resistances of the on-chip low-Q inductors into the noise optimization procedure explicitly. A 10-GHz LNA is designed and implemented in a standard mixed-signal/RF bulk 0.18-μm CMOS technology based on this formulation. The measurement results, with a power gain of 11.25 dB and a noise figure (NF) of 2.9 dB, show the lowest NF among the LNAs using bulk 0.18-μm CMOS at this frequency.

Original language	English
Pages (from-to)	1554-1559
Number of pages	6
Journal	IEEE Transactions on Microwave Theory and Techniques
Volume	54
Issue number	4
DOIs	https://doi.org/10.1109/TMTT.2006.871365
State	Published - 1 Apr 2006

Keywords

CMOS
Low-noise amplifier (LNA)

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abstract = "A noise optimization formulation for a CMOS low-noise amplifier (LNA) with on-chip low-Q inductors is presented, which incorporates the series resistances of the on-chip low-Q inductors into the noise optimization procedure explicitly. A 10-GHz LNA is designed and implemented in a standard mixed-signal/RF bulk 0.18-μm CMOS technology based on this formulation. The measurement results, with a power gain of 11.25 dB and a noise figure (NF) of 2.9 dB, show the lowest NF among the LNAs using bulk 0.18-μm CMOS at this frequency.",

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AU - Sun, Kuo Jung

AU - Tsai , Zuo-Min

AU - Lin, Kun You

AU - Wang, Huei

PY - 2006/4/1

Y1 - 2006/4/1

N2 - A noise optimization formulation for a CMOS low-noise amplifier (LNA) with on-chip low-Q inductors is presented, which incorporates the series resistances of the on-chip low-Q inductors into the noise optimization procedure explicitly. A 10-GHz LNA is designed and implemented in a standard mixed-signal/RF bulk 0.18-μm CMOS technology based on this formulation. The measurement results, with a power gain of 11.25 dB and a noise figure (NF) of 2.9 dB, show the lowest NF among the LNAs using bulk 0.18-μm CMOS at this frequency.

AB - A noise optimization formulation for a CMOS low-noise amplifier (LNA) with on-chip low-Q inductors is presented, which incorporates the series resistances of the on-chip low-Q inductors into the noise optimization procedure explicitly. A 10-GHz LNA is designed and implemented in a standard mixed-signal/RF bulk 0.18-μm CMOS technology based on this formulation. The measurement results, with a power gain of 11.25 dB and a noise figure (NF) of 2.9 dB, show the lowest NF among the LNAs using bulk 0.18-μm CMOS at this frequency.

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KW - Low-noise amplifier (LNA)

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JO - IEEE Transactions on Microwave Theory and Techniques

JF - IEEE Transactions on Microwave Theory and Techniques

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A noise optimization formulation for CMOS low-noise amplifiers with on-chip low-Q inductors

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Keywords

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