A new VLSI 2-D diagonal-symmetry filter architecture design

Pei Yu Chen*, Lan-Da Van, Hari C. Reddy, Chin-Teng Lin

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

12 Scopus citations

Abstract

In this paper, we propose two new two-dimensional (2-D) IIR and FIR filter architectures for 2-D transfer function with diagonal symmetry. The presented type-I structure with diagonal symmetry has the lowest number of multipliers, and zero latency without sacrificing the number of the delay elements. Importantly, the proposed type-II IIR filter possesses high speed, local broadcast, and the same number of multipliers and latency as the type I shows at expense of a slight increment of number of delay elements.

Original languageEnglish
Title of host publicationProceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Pages320-323
Number of pages4
DOIs
StatePublished - 1 Dec 2008
EventAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems - Macao, China
Duration: 30 Nov 20083 Dec 2008

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

ConferenceAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
CountryChina
CityMacao
Period30/11/083/12/08

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