A New Vertical Double Diffused MOSFET—The Self-Aligned Terraced-Gate MOSFET

Daisuke Ueda; Hiromitsu Takagi; Gota Kano

doi:10.1109/T-ED.1984.21543

A New Vertical Double Diffused MOSFET—The Self-Aligned Terraced-Gate MOSFET

Daisuke Ueda, Hiromitsu Takagi, Gota Kano

International College of Semiconductor Technology

Research output: Contribution to journal › Article › peer-review

17 Scopus citations

Abstract

A new power MOSFET structure with a Self-aligned Terraced Gate (STGMOSFET) is demonstrated. The unique gate structure of the STGMOSFET reduces the parasitic gate capacitances, resulting in improved high-frequency performance. The STGMOSFET structure was used to design a 3.5 mm X 3.5 mm transistor. This chip had an on-resistance of 2.3 n and a 500-V source- drain breakdown voltage. It exhibited excellent high-frequency performance with a cut-off frequency of 100 MHz, and rise and fall times of 5 and 20 nS, respectively.

Original language	English
Pages (from-to)	416-420
Number of pages	5
Journal	IEEE Transactions on Electron Devices
Volume	31
Issue number	4
DOIs	https://doi.org/10.1109/T-ED.1984.21543
State	Published - 1 Jan 1984

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