A new technique for hot carrier reliability evaluations of flash memory cell after long-term program/erase cycles

Steve S. Chung*, Cherng Ming Yih, Shui Ming Cheng, Mong Song Liang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

10 Scopus citations

Abstract

In this paper, we provide a methodology to evaluate the hot-carrier-induced reliability of flash memory cells after long-term program/erase cycles. First, the gated-diode measurement technique has been employed for determining the lateral distributions of interface state (N it ) and oxide trap charges (Q ox ) under both channel-hot-electron (CHE) programming bias and source-side erase-bias stress conditions. A gate current model was then developed by including both the effects of N it and Q ox . Degradation of flash memory cell after P/E cycles due to the above oxide damage was studied by monitoring the gate current. For the cells during programming, the oxide damage near the drain will result in a programming time delay, and we found that the interface state generation is the dominant mechanism. Furthermore, for the cells after long-term erase using source-side FN erase, the oxide trap charge will dominate the cell performance such as read-disturb. In order to reduce the read-disturb, source bias should be kept as low as possible since the larger the applied source erasing bias, the worse the device reliability becomes.

Original languageEnglish
Pages (from-to)1883-1889
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume46
Issue number9
DOIs
StatePublished - 1 Dec 1999

Keywords

  • Flash memory
  • Hot carrier reliability

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