A new RSA cryptosystem hardware design based on montgomery's algorithm

Ching Chao Yang*, Tian-Sheuan Chang, Chein Wei Jen

*Corresponding author for this work

Research output: Contribution to journalArticle

70 Scopus citations


In this paper, we propose a new algorithm based on Montgomery's algorithm to calculate modular multiplication that is the core arithmetic operation in an RSA cryptosystem. The modified algorithm eliminates over-large residue and has very short critical path delay that yields a very high-speed processing. The new architecture based on this modified algorithm takes about 1.5 n2 clock cycles on the average to finish one n-bit RSA operation. We have implemented a 512-bit single-chip RSA processor based on the modified algorithm with Compass 0.6-μm SPDM CMOS cell library. The simulation results show that the processor can operate up to 125 MHz and deliver the baud rate of 164 Kbits/s on the average.

Original languageEnglish
Pages (from-to)908-913
Number of pages6
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Issue number7
StatePublished - 1 Dec 1998

Fingerprint Dive into the research topics of 'A new RSA cryptosystem hardware design based on montgomery's algorithm'. Together they form a unique fingerprint.

  • Cite this