A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

Chung-Yu Wu*, Ming-Dou Ker, Chung Yuan Lee, Joe Ko, Larry Lin

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

A novel CMOS on-chip ESD (electrostatic discharge) protection circuit which consists of dual parasitic SCR structures is proposed. Experimental results show that it can successfully provide for negative and positive ESD protection with failure thresholds greater than ±1 kV and ±10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. Moreover, low triggering voltages in both SCRs can be readily achieved without involving device or junction breakdown.

Original languageEnglish
Title of host publicationProceedings of the Custom Integrated Circuits Conference
PublisherPubl by IEEE
ISBN (Print)0780300157
DOIs
StatePublished - 1 Dec 1991
EventProceedings of the IEEE 1991 Custom Integrated Circuits Conference - San Diego, CA, USA
Duration: 12 May 199115 May 1991

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Conference

ConferenceProceedings of the IEEE 1991 Custom Integrated Circuits Conference
CitySan Diego, CA, USA
Period12/05/9115/05/91

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    Wu, C-Y., Ker, M-D., Lee, C. Y., Ko, J., & Lin, L. (1991). A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI. In Proceedings of the Custom Integrated Circuits Conference (Proceedings of the Custom Integrated Circuits Conference). Publ by IEEE. https://doi.org/10.1109/CICC.1991.164085