Abstract
In this paper, the evidence of SiGe layer induced trap generation and its correlation with enhanced degradation in strained-Si/SiGe CMOS devices have been reported for the first time. First, a new two-level charge pumping(CP) curve has been demonstrated to identify the Ge out-diffusion effect. Secondly, enhanced degradation in strained-Si devices has been clarified based on experimental results. Both n- and p-MOSFE's exhibit different extent of HC degradation effect. This is attributed to the difference in their mobility enhancement as well as additional traps coming from the Si/SiGe interface. Finally, temperature dependence of HC and NBTI has been examined for both strained-Si and bulk devices. Sophisticated measurement techniques, charge pumping and gated-diode (GD) measurements, have been employed to understand the generated interface traps. Results show that strained-Si device is less sensitive to the temperature and has a chance for better NBTI reliability if we have a good control of the strained-Si/SiGe interface, such as through low temperature gate oxide process or better S/D junction formation.
Original language | English |
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Article number | 1469222 |
Pages (from-to) | 86-87 |
Number of pages | 2 |
Journal | Digest of Technical Papers - Symposium on VLSI Technology |
Volume | 2005 |
DOIs | |
State | Published - 1 Dec 2005 |
Event | 2005 Symposium on VLSI Technology - Kyoto, Japan Duration: 14 Jun 2005 → 14 Jun 2005 |
Keywords
- Charge-Pumping(CP)
- Gated-Diode(GD) methods
- Negative Bias Temperature Instability(NBTI)
- Strained-Si devices