A new high-performance CMOS GHz power amplifier design with common-mode signal cancellation technique

Chung-Yu Wu, Wen Chieh Wang, Tzung Ming Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This work describes a novel common-mode signal rejection method for power amplifiers. A power amplifier with standard 1P5M 0.25 μm CMOS technology was simulated and analyzed. This common-mode signal cancellation method makes the performance, in terms of output power and efficiency of the power amplifier, more immune to input common-mode signals than conventional power amplifiers. Simulated results indicate that this fully balanced differential power amplifier yields 24 dBm output power at 2.45 GHz, from a 3.3 V power supply. The simulated drain efficiency is 33.21%, and the overall power-added efficiency is 32.84%. The power amplifier is highly linear.

Original languageEnglish
Title of host publicationProceedings - APCCAS 2002
Subtitle of host publicationAsia-Pacific Conference on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages395-398
Number of pages4
ISBN (Electronic)0780376900
DOIs
StatePublished - 1 Jan 2002
EventAsia-Pacific Conference on Circuits and Systems, APCCAS 2002 - Denpasar, Bali, Indonesia
Duration: 28 Oct 200231 Oct 2002

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Volume2

Conference

ConferenceAsia-Pacific Conference on Circuits and Systems, APCCAS 2002
CountryIndonesia
CityDenpasar, Bali
Period28/10/0231/10/02

Keywords

  • Circuits
  • Degradation
  • Frequency
  • High power amplifiers
  • Power amplifiers
  • Power generation
  • Power harmonic filters
  • Radiofrequency amplifiers
  • Signal design
  • Voltage

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