A new general method to model signal timing of E/D NMOS logic

Chung-Yu Wu*, Yen‐Tai ‐T Lin

*Corresponding author for this work

Research output: Contribution to journalArticle

3 Scopus citations

Abstract

A new general modelling method for E/D NMOS logic is proposed and applied to the case of inverters. In this model, non‐linear device currents in the large‐signal equivalent circuit are reformulated by the curve‐fitting technique. Then output voltage wave‐forms are analytically solved region by region from the equivalent circuit. From the derived formulae, the rise/fall time and delay time can be calculated. Wide‐range comparisons with SPICE simulation results were performed to verify the accuracy and the general applicability of the developed model. Two examples are given to demonstrate the applications of the developed timing model to timing analysis. It is shown that the model has a good accuracy for E/D inverters with a wide range of beta ratios, gate sizes, capacitive loads, input voltage wave‐forms and device parameters. Moreover, the required CPU time and memory are small. These make the proposed modelling method an interesting approach to model E/D NMOS gates for CAD applications.

Original languageEnglish
Pages (from-to)447-464
Number of pages18
JournalInternational Journal of Circuit Theory and Applications
Volume17
Issue number4
DOIs
StatePublished - 1 Jan 1989

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