A new five-mask-count process for fabrication of pol y-si nanowire-channel cmos inverters

Chia Hao Kuo, Horng Chih Lin*, Tiao Yuan Huang

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

Abstract

A new five-mask-count process for fabricating CMOS inverters with poly-Si NW channels is demonstrated. The fabricated devices show reasonable symmetric driving current by well-designed structural parameters. From voltage transfer characteristics (VTC), an abrupt transition, large noise margins, and high voltage gain are obtained with a supply voltage of 5V.

Original languageEnglish
Pages (from-to)1086-1089
Number of pages4
JournalDigest of Technical Papers - SID International Symposium
Volume43
Issue number1
DOIs
StatePublished - 1 Jan 2012
Event49th SID International Symposium, Seminar and Exhibition, dubbed Display Week, 2012 - Boston, United States
Duration: 3 Jun 20128 Jun 2012

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