A new dynamic scaling FFT processor

Yu Wei Lin*, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

A new FFT processor with radix-8 algorithm and novel matrix buffer is presented in this paper. About 64 K bit memory can be saved in 8 K-point FFT by new dynamic scaling approach. Moreover, with data scheduling and prefetched buffering, single-port memory can be adopted in our FFT processor. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18 μm CMOS process with core area of 4.84mm2 and consumes only 25.2 mW at 20 MHz.

Original languageEnglish
Pages449-452
Number of pages4
StatePublished - 1 Dec 2004
Event2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
Duration: 6 Dec 20049 Dec 2004

Conference

Conference2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
CountryTaiwan
CityTainan
Period6/12/049/12/04

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