The design of a capacitor-ratio-independent algorithmic analog-to-digital converter (ADC) that is inherently insensitive to both capacitor ratio and amplifier offset voltage due to the use of switched-capacitor techniques is described. It can also be realized in a small chip area. This A/D converter completes n-bit conversion in 2n clock cycles, which is faster than previously reported converters. It is shown that the single-ended-output type of the ADC can achieve a 12-b resolution at a sampling rate of 42 kHz. SPICE simulations have been performed to verify the operation of this A/D converter.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1 Dec 1990|
|Event||1990 IEEE International Symposium on Circuits and Systems Part 3 (of 4) - New Orleans, LA, USA|
Duration: 1 May 1990 → 3 May 1990