A new architecture for charge pump circuit without suffering gate-oxide reliability in low-voltage CMOS processes

Tzu Ming Wang*, Wan Yi Shen, Ming-Dou Ker

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A new architecture of charge pump circuit without suffering gate-oxide reliability in low-voltage CMOS processes is proposed, which is composed of two identical pumping branches and four-phase clock signals. The four-phase clock signals are designed to have no undesirable return-back leakage path during clock transition and to control the charge transfer MOSFET switches in the proposed circuit to be turned on and off completely. Therefore, its pumping efficiency is higher than that of the conventional one. Because the gate-to-source and gate-to-drain voltages of all devices in the new proposed charge pump circuit do not exceed the normal power supply voltage (VDD), the new proposed charge pump circuit is suitable for applications in low-voltage CMOS processes.

Original languageEnglish
Title of host publicationICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems
Pages206-209
Number of pages4
DOIs
StatePublished - 1 Dec 2007
Event14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 - Marrakech, Morocco
Duration: 11 Dec 200714 Dec 2007

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Conference

Conference14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007
CountryMorocco
CityMarrakech
Period11/12/0714/12/07

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