A new analog implementation of the Kohonen neural network

Chung-Yu Wu; Wen Kai Kuo

doi:10.1109/VTSA.1993.263658

A new analog implementation of the Kohonen neural network

Chung-Yu Wu, Wen Kai Kuo

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

In this paper, a new circuit implementation of the Kohonen neural networks is proposed. A novel winner-take-all circuit is developed and digital counters are used to store and update the weights. An experimental chip of this system has been fabricated by 1.2um CMOS technology. A architecture is also proposed for these chips to be combined together to form a larger net.

Original language	English
Title of host publication	1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	262-266
Number of pages	5
ISBN (Electronic)	0780309782
DOIs	https://doi.org/10.1109/VTSA.1993.263658
State	Published - 1 Jan 1993
Event	1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Taipei, Taiwan Duration: 12 May 1993 → 14 May 1993

Publication series

Name	International Symposium on VLSI Technology, Systems, and Applications, Proceedings
ISSN (Print)	1930-8868

Conference

Conference	1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993
Country	Taiwan
City	Taipei
Period	12/05/93 → 14/05/93

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10.1109/VTSA.1993.263658

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Wu, C-Y., & Kuo, W. K. (1993). A new analog implementation of the Kohonen neural network. In 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers (pp. 262-266). [263658] (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VTSA.1993.263658

Wu, Chung-Yu ; Kuo, Wen Kai. / A new analog implementation of the Kohonen neural network. 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 1993. pp. 262-266 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

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abstract = "In this paper, a new circuit implementation of the Kohonen neural networks is proposed. A novel winner-take-all circuit is developed and digital counters are used to store and update the weights. An experimental chip of this system has been fabricated by 1.2um CMOS technology. A architecture is also proposed for these chips to be combined together to form a larger net.",

author = "Chung-Yu Wu and Kuo, {Wen Kai}",

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doi = "10.1109/VTSA.1993.263658",

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Wu, C-Y & Kuo, WK 1993, A new analog implementation of the Kohonen neural network. in 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers., 263658, International Symposium on VLSI Technology, Systems, and Applications, Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 262-266, 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993, Taipei, Taiwan, 12/05/93. https://doi.org/10.1109/VTSA.1993.263658

A new analog implementation of the Kohonen neural network. / Wu, Chung-Yu; Kuo, Wen Kai.

1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 1993. p. 262-266 263658 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, a new circuit implementation of the Kohonen neural networks is proposed. A novel winner-take-all circuit is developed and digital counters are used to store and update the weights. An experimental chip of this system has been fabricated by 1.2um CMOS technology. A architecture is also proposed for these chips to be combined together to form a larger net.

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Wu C-Y, Kuo WK. A new analog implementation of the Kohonen neural network. In 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 1993. p. 262-266. 263658. (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). https://doi.org/10.1109/VTSA.1993.263658

A new analog implementation of the Kohonen neural network

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