A trainable VLSI neuroprocessor for adaptive vector quantization based upon the frequency-sensitive competitive learning algorithm has been developed for high-speed high-ratio image compression applications. Simulation results show that such an algorithm is capable of producing goodquality reconstructed image at high compression ratios of more than 20. This neural network-based vector quantization design includes a fully parallel vector quantizer and a pipelined codebook generator which obtains a time complexity O(1) for each quantization vector. A 5x5-dimentional vector quantizer prototype chip has been designed, fabricated and tested. It contains 64 inner-product neural units and an extendable winner-take-all block. This mixed-signal chip occupies a compact silicon area of 4.6 x 6.8 mm2 in a 2.0-μm scalable CMOS technology. It provides a computing capability as high as 3.33 billion connections per second. It can achieve a speedup factor of 750 compared with a SUN-3/60 for a compression ratio of 33. Real-time adaptive VQ on industrial 1,024 × 1,024 pixel images is feasible using an extended array of such neuroprocessor chips. An industrial-scale chip of 125 mm2 size to achieve 104 billion connections per second for the 1024-codevector vector quantizer can be fabricated in a 1-μm CMOS technology.