This paper presents a near-threshold low-power all-digital PLL (ADPLL). It includes a 9-bit bootstrapped DCO (BDCO) to reduce supply voltage and power consumption, a weighted thermometer-controlled resistor network (WTRN) to achieve high linearity, and a 4-bit sigma-delta modulator to improve the resolution through dithering. The ADPLL is fabricated in a 90 nm SPRVT low-K CMOS process with a core area of 0.057 mm. The measured results demonstrate that the bootstrapped ring oscillator (BTRO) oscillates at 602 MHz under a supply of 0.5 V and consumes 49.1 μW. The ADPLL operates at 480 MHz (48 MHz) with a power consumption of 78 μW (2.4 μW) under a supply voltage of 0.5 V (0.25 V).
- All-digital phase-locked loop (ADPLL)
- bootstrapped circuit
- energy-efficient design
- near-threshold circuit