A NAND structured cell with a new programming technology for highly reliable 5V-only flash EEPROM

R. Kirisawa*, S. Aritome, R. Nakayama, T. Endoh, Riichiro Shirota, F. Masuoka

*Corresponding author for this work

Research output: Contribution to journalConference article

23 Scopus citations

Abstract

A programming technology is proposed to improve the endurance and read retention characteristics of NAND-structured EEPROM cells programmed by Fowler-Nordheim tunneling of electrons. Erasing and writing are accomplished uniformly over the whole channel area instead of nonuniform erasing at the drain. To achieve programming over the whole channel area, a new device structure is also proposed. The high-voltage pulses can be easily generated on a chip from a single 5-V power supply because the direct current due to the avalanche breakdown does not flow. The gate length of the memory transistor is 1.0 μm. Using 1.0 μm rules, the cell size per bit is 11.7 μm 2.

Original languageEnglish
Article number5727502
Pages (from-to)129-130
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
DOIs
StatePublished - 1 Dec 1990
Event1990 Symposium on VLSI Technology - Honolulu, HI, United States
Duration: 4 Jun 19907 Jun 1990

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