A multiple supply voltage based power reduction method in 3-D ICs considering process variations and thermal effects

Shih An Yu*, Pei Yu Huang, Yu-Min Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

In this paper, a grid-based multiple supply voltage(MSV) assignment method is presented to statistically minimize the total power consumption of 3-D IC. This method consists of a statistical electro-thermal simulator to get the mean and variance of on-chip, a thermal-aware statistical static timing analysis(SSTA) to take into account the thermal effect on circuit timing, the statistical power-delayjsensitivity-slack product to be the optimization criterion, and an incremental update of statistical timing to save the runtime. The experimental results demonstrate the effectiveness of the developed methodology and indicate that the consideration of the thermal effect in the circuit simulation is imperative.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2009
Subtitle of host publicationAsia and South Pacific Design Automation Conference 2009
Pages55-60
Number of pages6
DOIs
StatePublished - 20 Apr 2009
EventAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 - Yokohama, Japan
Duration: 19 Jan 200922 Jan 2009

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

ConferenceAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
CountryJapan
CityYokohama
Period19/01/0922/01/09

Fingerprint Dive into the research topics of 'A multiple supply voltage based power reduction method in 3-D ICs considering process variations and thermal effects'. Together they form a unique fingerprint.

Cite this