A multicycle communication architecture and synthesis flow for global interconnect resource sharing

Wei Sheng Huang*, Yu Ru Hong, Juinn-Dar Huang, Ya Shih Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

In deep submicron technology, wire delay is no longer negligible and is gradually dominating the system latency. Some state-of-the-art architectural synthesis flows adopt the distributed register (DR) architecture to cope with this increasing latency. The DR architecture, though allows multicycle communication, introduces extra overhead on interconnect resource. In this paper, we propose the Regular Distributed Register - Global Resource Sharing (RDR-GRS) architecture to enable global sharing of interconnects and registers. Based on the RDR-GRS architecture, we further define the channel and register allocation problem as a path scheduling problem of data transfers. A formal and flexible formulation of this problem is then presented and optimally solved by Integer Linear Programming (ILP). Experimental results show that RDR-GRS/ILP can av-eragely reduce 58% wires and 35% registers compared to the previous work.

Original languageEnglish
Title of host publication2008 Asia and South Pacific Design Automation Conference, ASP-DAC
Pages16-21
Number of pages6
DOIs
StatePublished - 21 Aug 2008
Event2008 Asia and South Pacific Design Automation Conference, ASP-DAC - Seoul, Korea, Republic of
Duration: 21 Mar 200824 Mar 2008

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2008 Asia and South Pacific Design Automation Conference, ASP-DAC
CountryKorea, Republic of
CitySeoul
Period21/03/0824/03/08

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