A multi-layer obstacles-avoiding router using X-architecture

Yu Cheng Lin*, Hsi An Chien, Chia Cheng Shih, Hung-Ming Chen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Scopus citations


In recent years, scaling down device dimension or utilizing novel crystallization technologies provide the opportunity of applying much more devices to integrated circuit fabrication. Due to emerging DSM effects, the research about routing has drawn much attention in VLSI Physical Design. In this paper, we will focus on three issues. One, the traditional Manhattan routing has longer length and larger delay than X-Architecture routing. Second, in multilayer routing, the delay of one via is much larger than the delay of Manhattan routing. Third, since a routed segment and macro cell should be considered as obstacles, we must consider the rectangle and non-rectangle obstacles, and consider the number of vias as well. Our algorithm can handle both rectangle obstacles and non-rectangle obstacles, and we use fewer vias and X-Architecture router by region to construct the multilayer routing trees. The main purpose is to obtain an obstacles-avoiding routing tree of minimal wire length and minimal delay.

Original languageEnglish
Pages (from-to)879-888
Number of pages10
JournalWSEAS Transactions on Circuits and Systems
Issue number8
StatePublished - 1 Dec 2008


  • Algorithm
  • Multi-layer
  • Physical design
  • Routing
  • VLSI
  • X-Architecture

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