A multi-bin constant throughput CABAC decoder for HEVC

Hsuan Ku Chen, Chih Chung Fang, Tian-Sheuan Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes a CABAC decoder for HEVC that achieves constant high throughput multi-bin decoding with the parallel syntax element parser to solve the dependency problem in the traditional prediction based multi-bin architecture. The hardware implementation with TSMC 90nm CMOS technology can process 1 bins per cycles with 48,430 gate count (270Mbins/sec,) or 3 bins per cycle with 209,422 gate count (810Mbins/sec) when operating at 270MHz.

Original languageEnglish
Title of host publication2015 IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies, AEECT 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479974313
DOIs
StatePublished - 17 Dec 2015
Event3rd IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies, AEECT 2015 - Amman, Jordan
Duration: 3 Nov 20155 Nov 2015

Publication series

Name2015 IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies, AEECT 2015

Conference

Conference3rd IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies, AEECT 2015
CountryJordan
CityAmman
Period3/11/155/11/15

Keywords

  • CABAC
  • Decoder
  • HEVC
  • VLSI

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