A multi-axis readout circuit using in female ovulation monitoring platform

Hsin Yi Yu, Kelvin Yi Tse Lai, Hsie-Chia Chang, Chen-Yi Lee

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this paper, an energy-efficient monitor, including three capacitive and two resistive readout circuits with hardware-sharing architecture, is presented for female ovulation. The proposed design is featuring two calibration modules: one decreases the initial offset by capacitor array, and the other reduces P-V-T variations by taking proportion between sensing and ruler results. After implemented in UMC 0.18μm CMOS-MEMS technology, the post-layout simulation results show that our circuit consumes 30μW and 49μW in 0.8ms conversion time under 1.8V supplied voltage for 1-axis and 3-axis. The capacitive resolution is around 0.1fF and the sensing range of die-temperature is 0~100°C with 0.05°C resolution.

Original languageEnglish
Title of host publication2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467394987
DOIs
StatePublished - 31 May 2016
Event2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan
Duration: 25 Apr 201627 Apr 2016

Publication series

Name2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Conference

Conference2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
CountryTaiwan
CityHsinchu
Period25/04/1627/04/16

Keywords

  • Capacitive and Resistive Readout Circuits
  • Female Ovulation Monitoring Platform
  • Time-to-Digital Converter

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